Technical Field
The present disclosure relates to integrated circuits (ICs). More specifically, the present disclosure relates to processes for creating and adjusting models of IC layouts.
Related Art
Fabrication foundries (“fabs”) can manufacture ICs using photolithographic processes. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating of a substrate. To fabricate an IC, photomasks are created using an IC layout as a template. The photomasks contain the various geometries (i.e., features) of the IC layout, and these geometries can be separated with layers of photoresist material. The various geometries contained on the photomasks correspond to the various base physical IC elements that make up functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with different conductive and insulating properties may be built up to form the overall IC and the circuits within the IC layout.
As integrated circuit (IC) components have continued to decrease in size, improvements to scale have spawned design implementation issues for some types of features, e.g., in complementary metal-oxide-semiconductor (CMOS) ICs with features sized less than approximately twenty-two nanometers (nm). As IC technology continues to shrink, the growing need for empirical data from a design may exacerbate the uncertainty of the manufacturing process, thereby increasing the risk of defects or impaired operability. Conventional approaches for traversing physical limits may apply manual or computer-implemented techniques for increasing the resolution of chips printed using optical lithography. One such technique is known as optical proximity correction (OPC). OPC is a computational method for correcting irregularities and distortions arising from diffraction effects by the transforming of mask geometries.
An OPC model of an IC layout may include one or more sub-resolution assist features (SRAFs), also known as “scattering bars,” solely to improve the printability of isolated features. SRAFs take advantage of the fact that an isolated feature in an OPC model will typically print at a feature size significantly different from similarly positioned features that are in close proximity with other features. An SRAF may be included in a mask near a relatively isolated target feature to affect the printing density of the target feature, e.g., to cause the targeted feature to behave more like a dense feature after being printed, and/or to change the position of the projected edges in the target feature. SRAFs are structured such that their intensity profiles are not below a threshold dose for fabricating an IC structure, and thus are considered to be “sub-resolution” features. The presence of an SRAF near the target feature will affect nearby printed features, without the SRAF actually being printed. Selecting positions for SRAF insertion into an IC layout can be time-consuming. In particular, SRAF insertion is conventionally performed via manual inspection and/or special case mathematical models due to substantial physical differences between features, IC layouts, products, etc. Conventional models do not offer a predictable and cost-effective way to automatically predict and select locations for SRAFs to improve the printability of nearby features.